1. Field of the Invention
The present invention relates to a new type of a semiconductor device, more particularly, to a semiconductor device having at least one transistor pair which, based upon a new operational principle, has a simplified constitution suitable for higher integration.
Hereinafter, the term "polycrystal" includes "amorphous", so far as it is not refused.
2. Description of the Related Art
In general, a bipolar transistor and a field effect transistor (FET) are mainly used as transistors in the prior art. In a highly integrated semiconductor device, an insulation gate type FET particularly is widely used.
Conventional technologies will be described with reference to FIGS. 1(A), 1(B) and 1(C).
FIG. 1(A) is a schematic view showing a structure of an insulation gate type FET in conventional technologies. In FIG. 1(A) a pair of n-type domains 62, 63 are formed on the surface of a p-type substrate 61, with a sandwiched channel region 64, to create a source/drain region. A gate electrode 67 is formed on the substrate 61 through an insulation film 66. Based on a voltage applied on the gate electrode 67, a channel region 64 is controlled to adjust a current path between source/drain regions 62 and 63.
FIG. 1(B) is a schematic view showing the operation of an FET shown in FIG. 1(A). A source region 62 is grounded and a positive potential is applied to a drain region 63. As the case may be, since a pn junction around the drain region 63 is adversely biased a depletion layer 65 is formed around the drain region 63.
When a positive potential is applied on a gate electrode 67, a hole in the channel region 64 is excluded by the positive potential to attract electrons. Thus, an n-channel is formed in the channel region 64. If the n-channel makes a source region 62 and a drain region 63 connect therewith, current flows between the source and the drain.
The n-channel FET is disck in FIG. 1(A) and FIG. 1(B) and when the conductivity type in each region is inverted, a p-channel FET is obtained. In the case of a p-channel FET, the polarity of applied voltage is inverted.
A flip-flop is constituted by means of cruciform wiring of four transistors. A memory element of an SRAM has a form such that transfer gates are connected to an interconnecting point of a flip-flop.
Fundamentally, four transistors are employed in the flip-flop and six transistors are employed in the static RAM (SRAM). From the stand point of high integration, it is required that these logic elements can be formed in a narrow area as much as possible.
FIG. 1(C) illustrates an example of an SRAM configuration for which a high integration is intended. A transistor T11 and a transistor T12 are series-connected at a connection node N1, and a transistor T13 and a transistor T14 are series-connected at a connection node N2. These connection nodes N1 and N2 are led outward via transfer gates T15 and T16, respectively. The node N1 is connected to each gate of a transistor T13 and a transistor T14, while the node N2 is connected to each gate of a transistor T11 and a transistor T12.
With respect to the structure of the device, transistors T11 and T13 are produced by a thin film transistor using polycrystalline silicon, in order to enhance integration.
That is, transistors T12, T14 and transistors T15, T16 are formed in a semiconductor substrate and load transistors T11 and T13 are formed in a polycrystalline silicon thin film formed on the semiconductor substrate. An adoption of such solid structure enables an enhancement of integration.
According to the prior art, it is necessary for one FET to be provided with three electrode regions, that is, a source, a drain and a gate. Accordingly, it is necessary to provide 3n electrode regions to produce n transistors.